0-In Announces New Products Based on Breakthrough Formal Verification Algorithms
Enhanced Assertion-Based Verification Suite Enables Systematic Method for Eliminating Bugs in IC Designs
SAN JOSE, Calif. - January 27, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced a suite of new products based on powerful new formal verification technologies that increase performance by more than 100X over the previous version. V2.0 of the 0-In Assertion-Based Verification (ABV) Suite combines simulation with static formal and dynamic formal verification to provide a broad solution for fast and thorough functional verification of complex ASICs and System-on-Chip (SoC) devices.
Advanced Technology Finds Tough Bugs Before Silicon
The 0-In ABV Suite provides development teams the power to answer two key questions about the verification process:
- Does the design meet the target specification?
- Have all the bugs been eliminated before tape-out?
0-In's ABV products answer these questions by enabling assertions to check all aspects of the design's behavior and to catch bugs at the earliest possible point in the verification process. 0-In's V2.0 ABV Suite includes two new formal verification products as well as enhancements to 0-In's dynamic formal verification technology that finds tough, corner-case bugs usually not found until chips are in the lab. The combined power of 0-In's products enables development teams to find bugs missed by every other verification method.
"Finding all bugs prior to tape-out is critical for competing in today's aggressive market environment," said Emil Girczyc, 0-In President and CEO. "V2.0 brings to market breakthrough formal verification algorithms that find the toughest bugs in complex designs before tape out. The power of these new algorithms leaves no place for bugs to hide, allowing design teams to meet aggressive time-to-market requirements."
New Products and Technology
0-In's V2.0 ABV Suite includes two new products, 0-In Checklist and 0-In Confirm, as well as new features and technology for all existing 0-In products.
0-In Checklist uses static netlist-analysis technology to rapidly and automatically find many common syntactic and semantic RTL coding errors, including simulation-to-synthesis mismatch errors, clock domain crossing errors, and others. 0-In Checklist is fast and easy to use, requiring no simulation and producing essentially no false error reports. Indeterminate assertions may be promoted to simulation and formal verification.
0-In Confirm finds deep RTL design bugs that are missed by all other verification methods. In particular, 0-In Confirm targets corner-case or worry-case assertions with deep counterexample (DCE) technology, a breakthrough exhaustive formal verification algorithm that is capable of finding bugs hundreds of cycles away from any selected simulation state. 0-In Confirm also can be used to verify that late-stage bug fixes are correct.
In V2.0, 0-In Search incorporates new algorithms that intelligently analyze and prioritize simulation cycles, increasing speed by 100X over previous releases and enabling users to apply dynamic formal verification across their entire regression suite. Simulation tests guide the formal algorithms to deep states, avoiding computational limitations. Dynamic formal verification technology then uses exhaustive formal algorithms to find bugs that simulation misses.
0-In Check includes the CheckerWare library, a rich library of over 70 Verilog assertion checkers that work in both simulation and formal verification and are testbench- and simulator-independent. V2.0 adds support for Accellera assertion standards, improves simulation performance and incorporates new coverage metrics for assertions.
The 0-In V2.0 ABV Suite provides value to designers and verification engineers throughout the entire development cycle, delivering a comprehensive assertion-based verification methodology that works from block-level through system-level verification, including regression testing, simulation acceleration, and hardware emulation. 0-In products are all simulator- and testbench-independent, making them applicable throughout the verification process. "Our new products are designed to address the customer's specific verification goals at each phase of the design cycle, no matter which vendor's tools are being used at each phase," noted Dr. Girczyc.
0-In supports Accellera assertion standards and 0-In products are interoperable with a wide range of tools from other EDA vendors.
Customers
ABV products from 0-In have been in production usage for nearly three years, which has generated feedback from numerous tape-outs and provided the impetus for V2 enhancements. 0-In's ABV tools are used today by leading design teams at AMD, Cisco Systems, Fujitsu, Hewlett Packard, LSI Logic, National Semiconductor, Nortel Networks, Sun Microsystems, and many other system and semiconductor suppliers.
"We've used 0-In products to catch design issues early and to improve the quality of our RTL," said Jonathan Sun, EDA Technologies Manager at Sun Microsystems, Inc., "V2.0 will enable us to further leverage the benefits of static and dynamic formal verification tools in our assertion-based verification flow."
"0-In tools are effective at finding tough, corner-case bugs that otherwise would go undetected," said Gordon Mortensen, Director of Engineering for the Internet Appliance Group at National Semiconductor. "On a recent SoC project, 0-In Search identified bugs that had a high probability of otherwise making it into silicon. We definitely had increased confidence after using the 0-In tools. That confidence was confirmed when the chip was fabricated and tested in the lab - we have not found any bugs in modules verified with 0-In."
Packaging, pricing, and availability
V2.0 of the 0-In ABV Suite products is available now. North American list prices for one-year time-based licenses are:
- 0-In Checklist -- $30K
- 0-In Check -- $15K
- 0-In Search -- $50K
- 0-In Confirm -- $75K
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
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0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.
Editorial Contacts:
0-In Design Automation
Steve White, 408-487-3649, swhite@0-in.com
Cayenne Communication
Linda Marchant, 919-403-7698, linda.marchant@cayennecom.com
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